The present invention relates generally to integrated circuit (IC) designs, and more particularly to a dual-port static random access memory (SRAM) cell with balanced performance between its read ports and write ports.
FIG. 1 schematically illustrates a typical dual-port SRAM cell 100 that is often used in memory devices for electronic products, such as cellular phones, digital cameras, personal digital assistants, and personal computers. The cell 100 includes two cross-coupled inverters 102 and 104. The inverter 102 is comprised of a pull-up p-type metal-oxide-semiconductor (PMOS) transistor 106 and a pull-down n-type metal-oxide-semiconductor (NMOS) transistor 108. The inverter 104 is comprised of a pull-up PMOS transistor 110 and a pull-down NMOS transistor 112. The sources of the PMOS transistors 106 and 110 are coupled to a power supply CVdd through a power line. The sources of the NMOS transistors 108 and 112 are coupled to a ground or a complementary power supply Vss through a complementary power line. The gates of PMOS transistor 106 and NMOS transistors 108 are connected together at a node 114, which is further connected to the drains of PMOS transistor 110 and NMOS transistor 112. The gates of PMOS transistor 110 and NMOS transistor 112 are connected together at node 116, which is further connected to the drains of PMOS transistor 106 and NMOS transistor 108. The cross-coupled first and second inverters 102 and 104 function as a latch that stores a value and its complement at the nodes 114 and 116, respectively.
A first write port pass gate transistor 120 is coupled between a write bit line (not shown in this figure) and the node 114. A second write port pass gate transistor 118 is coupled between a write bit line bar (not shown in this figure) and the node 116. A first read port pass gate transistor 122 is coupled between a read port bit line (not shown in this figure) and the node 116. A second read port pass gate transistor 124 is coupled between a second port bit line bar (not shown in the figure) and the node 114. The gates of the write pass gate transistors 118 and 120 are controlled by a write port word line WLA. The gates of the read pass gate transistors 122 and 124 are controlled by a read port word line WLB.
FIG. 2 illustrates a layout diagram 200 of the dual-port SRAM cell 100 shown in FIG. 1 on the substrate level. Referring to FIG. 1 and FIG. 2 simultaneously, the write port pass gate transistors 118 and 120 share the same write word line WLA over the oxide defined areas 202 and 204, respectively. Similarly, the read port pass gate transistors 122 and 124 share the same read word line WLB over the oxide defined areas 206 and 208, respectively. As shown in the drawing, the oxide define area 202 has a different shape from the oxide define area 204. As a result, the write port pass gate transistors 202 and 204 suffer from performance imbalance. Similarly, since the oxide defined areas 206 and 208 are also different in shape, the read port pass gate transistors 122 and 124 also suffer from performance imbalance.
FIG. 3 illustrates a layout diagram 300 of the dual-port SRAM cell 100, including the substrate level and the first metallization level. Referring to FIG. 1 and FIG. 3 simultaneously, the write port pass gate transistor 118 is connected to the read port pass gate transistor 122 via an interconnection structure 302. Because the transistors 118 and 122 are placed at two sides of the layout diagram 300, the interconnection structure 302 is rather long and space consuming. As a result, the conventional layout diagram 300 is not space efficient.
Thus, what is needed is a layout design for a dual-port SRAM cell that solves the performance imbalance issue and improves the space efficiency.